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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-20914-2E
FLASH MEMORY
CMOS
128 M (16M x 8/8M x 16) BIT
MirrorFlashTM*
MBM29PL12LM 10
DESCRIPTION
The MBM29PL12LM is a 128M-bit, 3.0 V-only Flash memory organized as 16M bytes by 8 bits or 8M words by 16 bits. The MBM29PL12LM is offered in 58-pin TSOP (1) and 80-ball FBGA. The device is designed to be programmed in-system with the standard 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. (Continued) MBM29PL12LM 10 3.0 V to 3.6 V 100 ns 100 ns 30 ns
PRODUCT LINE UP
Part No. VCC Max Address Access Time Max CE Access Time Max Page Read Access Time
Notes : * Programming in byte mode ( x 8) is prohibited. * Programming to the address that already contains data is prohibited. (It is mandatory to erase data prior to overprogram on the same address.)
PACKAGES
56-pin plastic TSOP (1) 80-ball plastic FBGA
(FPT-56P-M01)
(BGA-80P-M02)
* : MirrorFlashTM is a trademark of Fujitsu Limited.
MBM29PL12LM10
(Continued) The standard MBM29PL12LM offers access times of 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29PL12LM supports command set compatible with JEDEC single-power-supply EEPROMS standard. Commands are written into the command register. The register contents serve as input to an internal statemachine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29PL12LM is programmed by executing the program command sequence. This will invoke the Embedded Program AlgorithmTM which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase AlgorithmTM which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. All sectors are erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed, the devices internally return to the read mode. Fujitsu Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The devices electrically erase all bits within a sector simultaneously via hot-hole assisted erase. The words are programmed one word at a time using the EPROM programming mechanism of hot electron injection.
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MBM29PL12LM10
FEATURES
* 0.23 m Process Technology * Single 3.0 V read, program and erase Minimizes system level power requirements * Industry-standard pinouts 56-pin TSOP (1) 80-ball FBGA (Package suffix: PBT) * Minimum 100,000 program/erase cycles * High performance Page mode Fast 8 bytes / 4 words access capabililty * Sector erase architecture 256 x 64K byte and 32K word sectors Any combination of sectors can be concurrently erased. Also supports full chip erase * HiddenROM 256 bytes / 128 words of HiddenROM, accessible through a "HiddenROM Entry" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * WP/ACC input pin At VIL, allows protection of outermost two 8K bytes / 4K words sectors, regardless of sector protection/unprotection status At VACC, increases program performance * Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode * Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device * Low VCC write inhibit 2.5 V * Sector Group Protection Hardware method disables any combination of sector groups from program or erase operations * Sector Group Protection Set function by Extended sector protect command * Fast Programming Function by Extended Command * Temporary sector group unprotection Temporary sector group unprotection via the RESET pin This feature allows code changes in previously locked sectors * In accordance with CFI (Common Flash Memory Interface)
* : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
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MBM29PL12LM10
PIN ASSIGNMENTS
56-pin TSOP (1)
(Top View) N.C. A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET A21 WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 (Marking Side) 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 N.C. N.C. A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 N.C. VCCQ
FPT-56P-M01
80-ball FBGA
A8 * N.C. A7 * N.C. B8 * N.C. B7 * N.C. C8 * N.C. C7 A13 C6 A9 C5 D8 A22 D7 A12 D6 A8 D5 E8 F8 G8 VSS G7 H8 * N.C. H7 J8 * N.C. J7 K8 * N.C. K7 L8 * N.C. L7 * N.C. M8 * N.C. M7 * N.C.
* N.C. VCCQ E7 A14 E6 A10 E5 F7 A15 F6 A11 F5 A19 F4 A20 F3 A5 F2 A1 F1 * N.C.
A16 BYTE DQ15/A-1 VSS G6 H6 J6 K6 DQ6 K5 DQ4 K4 DQ3 K3 DQ1 K2 VSS K1 * N.C.
DQ7 DQ14 DQ13 G5 H5 J5 VCC J4
WE RESET A21 C4 D4 E4
DQ5 DQ12 G4 H4
RY/BY WP/ACC A18 C3 A7 A2 * N.C. A1 * N.C. B2 * N.C. B1 * N.C. C2 A3 C1 * N.C. D3 A17 D2 A4 D1 VCC E3 A6 E2 A2 E1 * N.C.
DQ2 DQ10 DQ11 G3 DQ0 G2 A0 G1 H3 DQ8 H2 CE H1 J3 DQ9 J2 OE J1 VSS
L2 * N.C. L1 * N.C.
M2 * N.C. M1 * N.C.
* N.C. VCCQ
BGA-80P-M02 4
MBM29PL12LM10
PIN DESCRIPTIONS
MBM29PL12LM Pin Configuration Pin A22 to A0, A-1 DQ15 to DQ0 CE OE WE WP/ACC RESET BYTE RY/BY VCC VCCQ VSS N.C. Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Hardware Write Protection/Program Acceleration Hardware Reset Pin/Temporary Sector Group Unprotection Select 8-bit or 16-bit mode Ready/Busy Output Device Power Supply Output Voltage Device Ground No Internal Connection Function
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MBM29PL12LM10
BLOCK DIAGRAM
DQ15 to DQ0
VCC VSS VCCQ
Erase Voltage Generator
Input/Output Buffers
WE RESET WP/ACC BYTE
State Control
Command Register
Program Voltage Generator
CE OE
Chip Enable Output Enable Logic
STB
Data Latch
STB
Y Decoder
Y Gating
Timer for Program/Erase A22 to A2 A1, A0 (A 1,)
Address Latch
X Decoder
Cell Matrix
LOGIC SYMBOL
A-1 23 A22 to A0 DQ 15 to DQ 0 CE OE WE WP/ACC RESET 16 or 8
BYTE VCCQ
RY/BY
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MBM29PL12LM10
DEVICE BUS OPERATION
MBM29PL12LM User Bus Operations (Word Mode : BYTE = VIH) Operation Standby Autoselect Manufacture Code*1 Autoselect Device Code*1 Read Output Disable Write (Program/Erase) Enable Sector Group Protection*2 Temporary Sector Group Unprotection Reset (Hardware) Sector Write Protection*3 CE OE WE H L L L L L L X X X X L L L H H H X X X X H H H H L L X X X A0 X L H A0 X A0 L X X X A1 X L L A1 X A1 H X X X A2 X L L A2 X A2 L X X X A3 X L L A3 X A3 L X X X A6 X L L A6 X A6 L X X X A9 X VID VID A9 X A9 X X X X DQ0 to DQ15 Hi-Z Code Code DOUT Hi-Z *4 *4 *4 Hi-Z X RESET H H H H H H VID VID L H WP/ ACC X X X X X *5 H H X L
Legend : L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. Hi-Z = High-Z, VID = 11.5 to 12.5V *1 : Manufacturer and device codes may also be accessed via a command register write sequence. See "MBM29PL12LM Standard Command Definitions". *2 : Refer to Sector Group Protection. *3 : Protects the first 32K words sector (SA0) *4 : DIN or DOUT as required by command sequence, data polling, or sector protect algorithm *5 : If WP/ACC = VIL, the first sector remain protected. If WP/ACC = VIH, the first sector will be protected or unprotected as determined by the method specified in "Sector Group Protection".
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MBM29PL12LM10
MBM29PL12LM User Bus Operations (Byte Mode : BYTE = VIL) Operation Standby Autoselect Manufacture Code*1 Autoselect Device Code*1 Read Output Disable Write (Erase) Enable Sector Group Protection*2 Temporary Sector Group Unprotection Reset (Hardware) Sector Write Protection*3 CE OE WE H L L L L L L X X X X L L L H H H X X X X H H H H L L X X X DQ15/ A0 A-1 X L L A-1 X A-1 L X X X X L H A0 X A0 L X X X A1 X L L A1 X A1 H X X X A2 X L L A2 X A2 L X X X A3 X L L A3 X A3 L X X X A6 X L L A6 X A6 L X X X A9 X VID VID A9 X A9 X X X X DQ0 to WP/ RESET DQ7 ACC Hi-Z Code Code DOUT Hi-Z *4 *4 *4 Hi-Z X H H H H H H VID VID L H X X X X X *5 H H X L
Legend : L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. Hi-Z = High-Z, VID = 11.5 to 12.5V *1 : Manufacturer and device codes may also be accessed via a command register write sequence. See "MBM29PL12LM Standard Command Definitions". *2 : Refer to Sector Group Protection. *3 : Protects the first 64K bytes sectors *4 : DIN or DOUT as required by command sequence, data polling, or sector protect algorithm *5 : If WP/ACC = VIL, the first sector remain protected. If WP/ACC = VIH, the first sector will be protected or unprotected as determined by the method specified in "Sector Group Protection".
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MBM29PL12LM10
MBM29PL12LM Standard Command Definitions*1 Command Sequence Reset*2 Reset*2 Autoselect (Device ID) Program Chip Erase Sector Erase
Word/ Byte Word Byte Word Byte Word Word Byte Word Byte
First Bus Second Bus Third Bus Bus Write Write Cycle Write Cycle Write Cycle Cycles Req'd Addr Data Addr -- 2AAh 555h 2AAh 555h Data -- 55h
Fourth Bus Read/Write Cycle Data --
Fifth Bus Sixth Bus Write Cycle Write Cycle Addr Data Addr Data -- -- -- -- -- -- -- --
Addr Data Addr -- 555h -- F0h --
1 3 3 4 6 6 1 1 3 2 2 20 1 3 4 1 3 4 4
XXXh F0h 555h AAAh 555h AAAh 555h 555h AAAh 555h AAAh AAh
AAAh 555h AAAh 555h 555h AAAh 555h AAAh -- -- 555h AAAh -- -- SA -- 555h AAAh SGA
RA*13 RD*13
AAh
55h 55h 55h
90h 00h*13 04h*13 A0h 80h PA 555h AAAh 555h AAAh -- -- -- -- -- SA -- -- SGA PD AAh
-- -- 2AAh 555h 2AAh 555h -- -- -- -- -- PA -- --
-- -- 55h
-- -- 555h AAAh SA -- -- -- -- -- WBL -- --
-- -- 10h
AAh 2AAh AAh 2AAh 555h 2AAh 555h -- -- 2AAh 555h PA
AAh
55h -- -- 55h PD
80h -- -- 20h -- -- 25h -- F0h
AAh -- -- -- -- -- 0Fh -- --
55h -- -- -- -- -- PD -- --
30h -- -- -- -- -- PD -- --
Program/Erase Suspend*3 Program/Erase Resume*3 Set to Fast Mode*4 Fast Program*4 Reset from Fast Mode*5 Write to Buffer
Word Byte Word Word/ Byte Word Byte
XXXh B0h XXXh 30h 555h AAAh AAh
XXXh A0h
XXXh 90h XXXh 00h*12 555h AAAh SA 555h AAAh AAh 29h AAh 2AAh 555h -- 2AAh 555h SGA 55h -- 55h
Program Buffer to Flash (Confirm) Write to Buffer Abort Reset*6
Extended Sector Group Protection*7,*8
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
XXXh 60h 55h AAh 555h AAAh 555h AAAh 555h AAAh
60h
40h
*13
--
SD*13
--
--
--
--
Query*9 HiddenROM Entry*10 HiddenROM Program *10,*11 HiddenROM Exit*11
98h
-- 2AAh 555h 2AAh 555h 2AAh 555h
--
-- 555h AAAh 555h AAAh 555h AAAh
--
--
--
--
--
--
AAh
55h
88h
--
--
--
--
--
--
AAh
55h
A0h
PA
PD
--
--
--
--
AAh
55h
90h
XXXh
00h
--
--
--
--
(Continued)
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MBM29PL12LM10
(Continued) Legend : Address bits A22 to A15 = X = "H" or "L" for all address commands except for Program Address (PA), Sector Address (SA) and Sector Group Address (SGA). Bus operations are defined in "MBM29PL12LM User Bus Operations (Word Mode : BYTE = VIH)" and "MBM29PL12LM User Bus Operations (Byte Mode : BYTE = VIL)". RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be programmed / erased. The combination of A22, A21, A20, A19, A18, A17, A16, and A15 will uniquely select any sector. See "Sector Address Table (MBM29PL12LM)". SGA = Sector Group Address to be protected. See "Sector Group Address Table (MBM29PL12LM)". RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of write plus. WBL = Write Buffer Location HRA = Address of the HiddenROM area ; Word Mode : 000000h to 000007h Byte Mode : 000000h to 0000FFh *1 : The command combinations not described in "MBM29PL12LM Standard Command Definitions" are illegal. *2 : Both of these reset commands are equivalent except for "Write to Buffer Abort Reset". *3 : The Erase Suspend and Erase Resume command are valid only during a sector erase operation. *4 : The Set to Fast Mode command is required prior to the Fast Program command. *5 : The Reset from Fast Mode command is required to return to the read mode when the device is in fast mode. *6 : Reset to the read mode. The Write to Buffer Abort Reset command is required after the Write to Buffer operation was aborted. *7 : This command is valid while RESET = VID. *8 : Sector Group Address (SGA) with A6 = 0, A3 = 0, A2 = 0, A1 = 1, and A0 = 0 *9 : The valid address are A6 to A0. *10 : The HiddenROM Entry command is required prior to the HiddenROM programming. *11 : This command is valid during HiddenROM mode. *12 : The data "F0h" is also acceptable. *13 : Indicates read cycle.
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MBM29PL12LM10
Sector Group Protection Verify Autoselect Codes Type Manufacturer's Code Device Code Word Byte Word Extended Device Code*2 Byte Word Byte Sector Group Protection*4 *1 : A-1 is for Byte mode. *2 : At Word mode, a read cycle at address 01h ( at Byte mode, 02h ) outputs device code. When 227Eh ( at Byte mode, 7Eh ) is output, it indicates that reading two additional codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these Extended Device Codes at the address of 0Eh ( at Byte mode, 1Ch ), as well as at 0Fh ( at Byte mode, 1Eh ). *3 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *4 : At CE = Fix, designate SGA as (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , with an interval of one cycle after WE rising (the
last write command) .
A22 to A15 X X X X Sector Group Addresses
A6 VIL VIL VIL VIL VIL
A3 VIL VIL VIH VIH VIL
A2 VIL VIL VIH VIH VIL
A1 VIL VIL VIH VIH VIH
A0 VIL VIH VIL VIH VIL
A-1*1 VIL X VIL X VIL X VIL VIL
Code (HEX) 04h 227Eh 7Eh 2212h 12h 2200h 00h *3
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MBM29PL12LM10
Sector Address Table (MBM29PL12LM)
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 A22 A21 A20 A19 A18 A17 A16 A15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Sector size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 000000h to 00FFFFh 010000h to 01FFFFh 020000h to 02FFFFh 030000h to 03FFFFh 040000h to 04FFFFh 050000h to 05FFFFh 060000h to 06FFFFh 070000h to 07FFFFh 080000h to 08FFFFh 090000h to 09FFFFh 0A0000h to 0AFFFFh 0B0000h to 0BFFFFh 0C0000h to 0CFFFFh 0D0000h to 0DFFFFh 0E0000h to 0EFFFFh 0F0000h to 0FFFFFh 100000h to 10FFFFh 110000h to 11FFFFh 120000h to 12FFFFh 130000h to 13FFFFh 140000h to 14FFFFh 150000h to 15FFFFh 160000h to 16FFFFh 170000h to 17FFFFh 180000h to 18FFFFh 190000h to 19FFFFh 1A0000h to 1AFFFFh 1B0000h to 1BFFFFh 1C0000h to 1CFFFFh 1D0000h to 1DFFFFh 1E0000h to 1EFFFFh (x16) Address Range 000000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh (Continued)
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MBM29PL12LM10
Sector SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62
A22 A21 A20 A19 A18 A17 A16 A15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Sector size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
(x8) Address Range 1F0000h to 1FFFFFh 200000h to 20FFFFh 210000h to 21FFFFh 220000h to 22FFFFh 230000h to 23FFFFh 240000h to 24FFFFh 250000h to 25FFFFh 260000h to 26FFFFh 270000h to 27FFFFh 280000h to 28FFFFh 290000h to 29FFFFh 2A0000h to 2AFFFFh 2B0000h to 2BFFFFh 2C0000h to 2CFFFFh 2D0000h to 2DFFFFh 2E0000h to 2EFFFFh 2F0000h to 2FFFFFh 300000h to 30FFFFh 310000h to 31FFFFh 320000h to 32FFFFh 330000h to 33FFFFh 340000h to 34FFFFh 350000h to 35FFFFh 360000h to 36FFFFh 370000h to 37FFFFh 380000h to 38FFFFh 390000h to 39FFFFh 3A0000h to 3AFFFFh 3B0000h to 3BFFFFh 3C0000h to 3CFFFFh 3D0000h to 3DFFFFh 3E0000h to 3EFFFFh
(x16) Address Range 0F8000h to 0FFFFFh 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh (Continued)
13
MBM29PL12LM10
Sector SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94
A22 A21 A20 A19 A18 A17 A16 A15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Sector size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
(x8) Address Range 3F0000h to 3FFFFFh 400000h to 40FFFFh 410000h to 41FFFFh 420000h to 42FFFFh 430000h to 43FFFFh 440000h to 44FFFFh 450000h to 45FFFFh 460000h to 46FFFFh 470000h to 47FFFFh 480000h to 48FFFFh 490000h to 49FFFFh 4A0000h to 4AFFFFh 4B0000h to 4BFFFFh 4C0000h to 4CFFFFh 4D0000h to 4DFFFFh 4E0000h to 4EFFFFh 4F0000h to 4FFFFFh 500000h to 50FFFFh 510000h to 51FFFFh 520000h to 52FFFFh 530000h to 53FFFFh 540000h to 54FFFFh 550000h to 55FFFFh 560000h to 56FFFFh 570000h to 57FFFFh 580000h to 58FFFFh 590000h to 59FFFFh 5A0000h to 5AFFFFh 5B0000h to 5BFFFFh 5C0000h to 5CFFFFh 5D0000h to 5DFFFFh 5E0000h to 5EFFFFh
(x16) Address Range 1F8000h to 1FFFFFh 200000h to 207FFFh 208000h to 20FFFFh 210000h to 217FFFh 218000h to 21FFFFh 220000h to 227FFFh 228000h to 22FFFFh 230000h to 237FFFh 238000h to 23FFFFh 240000h to 247FFFh 248000h to 24FFFFh 250000h to 257FFFh 258000h to 25FFFFh 260000h to 267FFFh 268000h to 26FFFFh 270000h to 277FFFh 278000h to 27FFFFh 280000h to 287FFFh 288000h to 28FFFFh 290000h to 297FFFh 298000h to 29FFFFh 2A0000h to 2A7FFFh 2A8000h to 2AFFFFh 2B0000h to 2B7FFFh 2B8000h to 2BFFFFh 2C0000h to 2C7FFFh 2C8000h to 2CFFFFh 2D0000h to 2D7FFFh 2D8000h to 2DFFFFh 2E0000h to 2EE7FFh 2E8000h to 2EFFFFh 2F0000h to 2F7FFFh (Continued)
14
MBM29PL12LM10
Sector SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124
A22 A21 A20 A19 A18 A17 A16 A15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Sector size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
(x8) Address Range 5F0000h to 5FFFFFh 600000h to 60FFFFh 610000h to 61FFFFh 620000h to 62FFFFh 630000h to 63FFFFh 640000h to 64FFFFh 650000h to 65FFFFh 660000h to 66FFFFh 670000h to 67FFFFh 680000h to 68FFFFh 690000h to 69FFFFh 6A0000h to 6AFFFFh 6B0000h to 6BFFFFh 6C0000h to 6CFFFFh 6D0000h to 6DFFFFh 6E0000h to 6EFFFFh 6F0000h to 6FFFFFh 700000h to 70FFFFh 710000h to 71FFFFh 720000h to 72FFFFh 730000h to 73FFFFh 740000h to 74FFFFh 750000h to 75FFFFh 760000h to 76FFFFh 770000h to 77FFFFh 780000h to 78FFFFh 790000h to 79FFFFh 7A0000h to 7AFFFFh 7B0000h to 7BFFFFh 7C0000h to 7CFFFFh
(x16) Address Range 2F8000h to 2FFFFFh 300000h to 307FFFh 308000h to 30FFFFh 310000h to 317FFFh 318000h to 31FFFFh 320000h to 327FFFh 328000h to 32FFFFh 330000h to 337FFFh 338000h to 33FFFFh 340000h to 347FFFh 348000h to 34FFFFh 350000h to 357FFFh 358000h to 35FFFFh 360000h to 367FFFh 368000h to 36FFFFh 370000h to 377FFFh 378000h to 37FFFFh 380000h to 387FFFh 388000h to 38FFFFh 390000h to 397FFFh 398000h to 39FFFFh 3A0000h to 3A7FFFh 3A8000h to 3AFFFFh 3B0000h to 3B7FFFh 3B8000h to 3BFFFFh 3C0000h to 3C7FFFh 3C8000h to 3CFFFFh 3D0000h to 3D7FFFh 3D8000h to 3DFFFFh 3E0000h to 3E7FFFh (Continued)
15
MBM29PL12LM10
Sector SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155
A22 A21 A20 A19 A18 A17 A16 A15 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Sector size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
(x8) Address Range 7D0000h to 7DFFFFh 7E0000h to 7EFFFFh 7F0000h to 7FFFFFh 800000h to 80FFFFh 810000h to 81FFFFh 820000h to 82FFFFh 830000h to 83FFFFh 840000h to 84FFFFh 850000h to 85FFFFh 860000h to 86FFFFh 870000h to 87FFFFh 880000h to 88FFFFh 890000h to 89FFFFh 8A0000h to 8AFFFFh 8B0000h to 8BFFFFh 8C0000h to 8CFFFFh 8D0000h to 8DFFFFh 8E0000h to 8EFFFFh 8F0000h to 8FFFFFh 900000h to 90FFFFh 910000h to 91FFFFh 920000h to 92FFFFh 930000h to 93FFFFh 940000h to 94FFFFh 950000h to 95FFFFh 960000h to 96FFFFh 970000h to 97FFFFh 980000h to 98FFFFh 990000h to 99FFFFh 9A0000h to 9AFFFFh 9B0000h to 9BFFFFh
(x16) Address Range 3E8000h to 3EFFFFh 3F0000h to 3F7FFFh 3F8000h to 3FFFFFh 400000h to 407FFFh 408000h to 40FFFFh 410000h to 417FFFh 418000h to 41FFFFh 420000h to 427FFFh 428000h to 42FFFFh 430000h to 437FFFh 438000h to 43FFFFh 440000h to 447FFFh 448000h to 44FFFFh 450000h to 457FFFh 458000h to 45FFFFh 460000h to 467FFFh 468000h to 46FFFFh 470000h to 477FFFh 478000h to 47FFFFh 480000h to 487FFFh 488000h to 48FFFFh 490000h to 497FFFh 498000h to 49FFFFh 4A0000h to 4A7FFFh 4A8000h to 4AFFFFh 4B0000h to 4B7FFFh 4B8000h to 4BFFFFh 4C0000h to 4C7FFFh 4C8000h to 4CFFFFh 4D0000h to 4D7FFFh 4D8000h to 4DFFFFh (Continued)
16
MBM29PL12LM10
Sector SA156 SA157 SA158 SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185
A22 A21 A20 A19 A18 A17 A16 A15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Sector size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
(x8) Address Range 9C0000h to 9CFFFFh 9D0000h to 9DFFFFh 9E0000h to 9EFFFFh 9F0000h to 9FFFFFh A00000h to A0FFFFh A10000h to A1FFFFh A20000h to A2FFFFh A30000h to A3FFFFh A40000h to A4FFFFh A50000h to A5FFFFh A60000h to A6FFFFh A70000h to A7FFFFh A80000h to A8FFFFh A90000h to A9FFFFh AA0000h to AAFFFFh AB0000h to ABFFFFh AC0000h to ACFFFFh AD0000h to ADFFFFh AE0000h to AEFFFFh AF0000h to AFFFFFh B00000h to B0FFFFh B10000h to B1FFFFh B20000h to B2FFFFh B30000h to B3FFFFh B40000h to B4FFFFh B50000h to B5FFFFh B60000h to B6FFFFh B70000h to B7FFFFh B80000h to B8FFFFh B90000h to B9FFFFh
(x16) Address Range 4E0000h to 4E7FFFh 4E8000h to 4EFFFFh 4F0000h to 4F7FFFh 4F8000h to 4FFFFFh 500000h to 507FFFh 508000h to 50FFFFh 510000h to 517FFFh 518000h to 51FFFFh 520000h to 527FFFh 528000h to 52FFFFh 530000h to 537FFFh 538000h to 53FFFFh 540000h to 547FFFh 548000h to 54FFFFh 550000h to 557FFFh 558000h to 55FFFFh 560000h to 567FFFh 568000h to 56FFFFh 570000h to 577FFFh 578000h to 57FFFFh 580000h to 587FFFh 588000h to 58FFFFh 590000h to 597FFFh 598000h to 59FFFFh 5A0000h to 5A7FFFh 5A8000h to 5AFFFFh 5B0000h to 5B7FFFh 5B8000h to 5BFFFFh 5C0000h to 5C7FFFh 5C8000h to 5CFFFFh (Continued)
17
MBM29PL12LM10
Sector SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 SA214 SA215
A22 A21 A20 A19 A18 A17 A16 A15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Sector size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
(x8) Address Range BA0000h to BAFFFFh BB0000h to BBFFFFh BC0000h to BCFFFFh BD0000h to BDFFFFh BE0000h to BEFFFFh BF0000h to BFFFFFh C00000h to C0FFFFh C10000h to C1FFFFh C20000h to C2FFFFh C30000h to C3FFFFh C40000h to C4FFFFh C50000h to C5FFFFh C60000h to C6FFFFh C70000h to C7FFFFh C80000h to C8FFFFh C90000h to C9FFFFh CA0000h to CAFFFFh CB0000h to CBFFFFh CC0000h to CCFFFFh CD0000h to CDFFFFh CE0000h to CEFFFFh CF0000h to CFFFFFh D00000h to D0FFFFh D10000h to D1FFFFh D20000h to D2FFFFh D30000h to D3FFFFh D40000h to D4FFFFh D50000h to D5FFFFh D60000h to D6FFFFh D70000h to D7FFFFh
(x16) Address Range 5D0000h to 5D7FFFh 5D8000h to 5DFFFFh 5E0000h to 5E7FFFh 5E8000h to 5EFFFFh 5F0000h to 5F7FFFh 5F8000h to 5FFFFFh 600000h to 607FFFh 608000h to 60FFFFh 610000h to 617FFFh 618000h to 61FFFFh 620000h to 627FFFh 628000h to 62FFFFh 630000h to 637FFFh 638000h to 63FFFFh 640000h to 647FFFh 648000h to 64FFFFh 650000h to 657FFFh 658000h to 65FFFFh 660000h to 667FFFh 668000h to 66FFFFh 670000h to 677FFFh 678000h to 67FFFFh 680000h to 687FFFh 688000h to 68FFFFh 690000h to 697FFFh 698000h to 69FFFFh 6A0000h to 6A7FFFh 6A8000h to 6AFFFFh 6B0000h to 6B7FFFh 6B8000h to 6BFFFFh (Continued)
18
MBM29PL12LM10
Sector SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230 SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245
A22 A21 A20 A19 A18 A17 A16 A15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Sector size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
(x8) Address Range D80000h to D8FFFFh D90000h to D9FFFFh DA0000h to DAFFFFh DB0000h to DBFFFFh DC0000h to DCFFFFh DD0000h to DDFFFFh DE0000h to DEFFFFh DF0000h to DFFFFFh E00000h to E0FFFFh E10000h to E1FFFFh E20000h to E2FFFFh E30000h to E3FFFFh E40000h to E4FFFFh E50000h to E5FFFFh E60000h to E6FFFFh E70000h to E7FFFFh E80000h to E8FFFFh E90000h to E9FFFFh EA0000h to EAFFFFh EB0000h to EBFFFFh EC0000h to ECFFFFh ED0000h to EDFFFFh EE0000h to EEFFFFh EF0000h to EFFFFFh F00000h to F0FFFFh F10000h to F1FFFFh F20000h to F2FFFFh F30000h to F3FFFFh F40000h to F4FFFFh F50000h to F5FFFFh
(x16) Address Range 6C0000h to 6C7FFFh 6C8000h to 6CFFFFh 6D0000h to 6D7FFFh 6D8000h to 6DFFFFh 6E0000h to 6E7FFFh 6E8000h to 6EFFFFh 6F0000h to 6F7FFFh 6F8000h to 6FFFFFh 700000h to 707FFFh 708000h to 70FFFFh 710000h to 717FFFh 718000h to 71FFFFh 720000h to 727FFFh 728000h to 72FFFFh 730000h to 737FFFh 738000h to 73FFFFh 740000h to 747FFFh 748000h to 74FFFFh 750000h to 757FFFh 758000h to 75FFFFh 760000h to 767FFFh 768000h to 76FFFFh 770000h to 777FFFh 778000h to 77FFFFh 780000h to 787FFFh 788000h to 78FFFFh 790000h to 797FFFh 798000h to 79FFFFh 7A0000h to 7A7FFFh 7A8000h to 7AFFFFh (Continued)
19
MBM29PL12LM10
(Continued) Sector SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 A22 A21 A20 A19 A18 A17 A16 A15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Sector size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range F60000h to F6FFFFh F70000h to F7FFFFh F80000h to F8FFFFh F90000h to F9FFFFh (x16) Address Range 7B0000h to 7B7FFFh 7B8000h to 7BFFFFh 7C0000h to 7C7FFFh 7C8000h to 7CFFFFh
FA0000h to FAFFFFh 7D0000h to 7D7FFFh FB0000h to FBFFFFh 7D8000h to 7DFFFFh FC0000h to FCFFFFh 7E0000h to 7E7FFFh FD0000h to FDFFFFh 7E8000h to 7EFFFFh FE0000h to FEFFFFh FF0000h to FFFFFFh 7F0000h to 7F7FFFh 7F8000h to 7FFFFFh
Note : The address range is A22 to A-1 if in Byte mode (BYTE = VIL) . The address range is A22 to A0 if in Word mode (BYTE = VIH) .
20
MBM29PL12LM10
Sector Group Address Table (MBM29PL12LM) Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 SGA25 SGA26 SGA27 SGA28 SGA29 SGA30 SGA31 SGA32 SGA33 SGA34 A22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A18 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A17 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A16 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A15 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sector group size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 Sectors SA0 SA1 SA2 SA3 SA4 to SA7 SA8 to SA11 SA12 to SA15 SA16 to SA19 SA20 to SA23 SA24 to SA27 SA28 to SA31 SA32 to SA35 SA36 to SA39 SA40 to SA43 SA44 to SA47 SA48 to SA51 SA52 to SA55 SA56 to SA59 SA60 to SA63 SA64 to SA67 SA68 to SA71 SA72 to SA75 SA76 to SA79 SA80 to SA83 SA84 to SA87 SA88 to SA91 SA92 to SA95 SA96 to SA99 SA100 to SA103 SA104 to SA107 SA108 to SA111 SA112 to SA115 SA116 to SA119 SA120 to SA123 SA124 to SA127 (Continued)
21
MBM29PL12LM10
(Continued) Sector Group SGA35 SGA36 SGA37 SGA38 SGA39 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47 SGA48 SGA49 SGA50 SGA51 SGA52 SGA53 SGA54 SGA55 SGA56 SGA57 SGA58 SGA59 SGA60 SGA61 SGA62 SGA63 SGA64 SGA65 SGA66 SGA67 SGA68 SGA69 A22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 A18 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 A17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 A16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 A15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Sector group size (Kbytes/Kwords) 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 256/128 64/32 64/32 64/32 64/32 Sectors SA128 to SA131 SA132 to SA135 SA136 to SA139 SA140 to SA143 SA144 to SA147 SA148 to SA151 SA152 to SA155 SA156 to SA159 SA160 to SA163 SA164 to SA167 SA168 to SA171 SA172 to SA175 SA176 to SA179 SA180 to SA183 SA184 to SA187 SA188 to SA191 SA192 to SA195 SA196 to SA199 SA200 to SA203 SA204 to SA207 SA208 to SA211 SA212 to SA215 SA216 to SA219 SA220 to SA223 SA224 to SA227 SA228 to SA231 SA232 to SA235 SA236 to SA239 SA240 to SA243 SA244 to SA247 SA248 to SA251 SA252 SA253 SA254 SA255
22
MBM29PL12LM10
Common Flash Memory Interface Code A0 to A6 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh DQ0 to DQ15 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h 0027h Description Query-unique ASCII string "QRY" Primary OEM Command Set (02h = Fujitsu standard) Address for Primary Extended Table Alternate OEM Command Set (00h = not applicable) Address for Alternate OEM Extended Table (00h = not applicable) VCC Min (write/erase) DQ7 to DQ4: 1V/bit, DQ3 to DQ0: 100 mV/bit VCC Max (write/erase) DQ7 to DQ4: 1V/bit, DQ3 to DQ0: 100 mV/bit VPP Min voltage (00h = no Vpp pin) VPP Max voltage (00h =no Vpp pin) Typical timeout per single write 2N s Typical timeout for Min size buffer write 2N s Typical timeout per individual sector erase 2N ms Typical timeout for full chip erase 2N ms Max timeout for write 2N times typical Max timeout for buffer write 2N times typical Max timeout per individual sector erase 2N times typical Max timeout for full chip erase 2N times typical Device Size = 2N byte Flash Device Interface description 02h : x 8/ x 16 Max number of byte in multi-byte write = 2N Number of Erase Block Regions within device (02h = Boot)
1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h
0036h 0000h 0000h 0007h 0007h 000Ah 0000h 0001h 0005h 0004h 0000h 0018h 0002h 0000h 0005h 0000h 0002h 007Fh 0000h 0020h 0000h 003Eh 0000h 0000h 0001h
Erase Block Region 1 Information
Erase Block Region 2 Information
(Continued) 23
MBM29PL12LM10
(Continued) A0 to A6 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch
DQ0 to DQ15 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0050h 0052h 0049h 0031h 0033h 0008h 0002h 0001h 0001h 0004h 0000h 0000h 0001h
Description
Erase Block Region 3 Information
Erase Block Region 4 Information
Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock Required Erase Suspend (02h = To Read & Write) Number of sectors in per group Sector Temporary Unprotection (01h = Supported) Sector Group Protection Algorithm Dual Operation (00h = Not Supported) Burst Mode Type (00h = Not Supported) Page Mode Type (01h = 4-Word Page Supported) VACC (Acceleration) Supply Minimum DQ7 to DQ4: 1V/bit, DQ3 to DQ0: 100mV/bit VACC (Acceleration) Supply Maximum DQ7 to DQ4: 1V/bit, DQ3 to DQ0: 100mV/bit CFI Write Protect (04h = Uniform Sectors Bottom Write Protection) Program Suspend (01h = Supported)
4Dh
00B5h
4Eh
00C5h
4Fh 50h
00XXh 01h
24
MBM29PL12LM10
FUNCTIONAL DESCRIPTION
Standby Mode There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and the other via the RESET pin only. When using both pins, CMOS standby mode is achieved with CE and RESET input held at VCC 0.3 V. Under this condition the current consumed is less than 5 A Max. During Embedded Algorithm operation, VCC active current (ICC2) is required even when CE = "H". The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, CMOS standby mode is achieved with RESET input held at VSS 0.3 V (CE = "H" or "L") . Under this condition the current consumed is less than 5 A Max. Once the RESET pin is set high, the device requires tRH as a wake-up time for output to be valid for read access. During standby mode, the output is in the high impedance state, regardless of OE input. Automatic Sleep Mode Automatic sleep mode works to restrain power consumption during read-out of device data. It can be useful in applications such as handy terminal, which requires low power consumption. To activate this mode, the device automatically switch themselves to low power mode when the device addresses remain stable after 30 ns from data valid. It is not necessary to control CE, WE, and OE in this mode. The current consumed is typically 1 A (CMOS Level). Since the data are latched during this mode, the data are continuously read out. When the addresses are changed, the mode is automatically canceled and the device read-out the data for changed addresses. Autoselect The Autoselect mode allows reading out of a binary code and identifies its manufacturer and type.It is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. To activate this mode, the programming equipment must force VID on address pin A9. Three identifier bytes may then be sequenced from the devices outputs by toggling A0. All addresses can be either High or Low except A6, A3,A2,A1 and A0. See "MBM29PL12LM User Bus Operations (Word Mode : BYTE = VIH)" and "MBM29PL12LM User Bus Operations (Byte Mode : BYTE = VIL)" in DEVICE BUS OPERATION. The manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in "MBM29PL12LM Standard Command Definitions" in DEVICE BUS OPERATION. Refer to Autoselect Command section. In Word mode, a read cycle from address 00h returns the manufacturer's code (Fujitsu = 04h) . A read cycle at address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes at addresses of 0Eh and 0Fh. Notice that the above applies to Word mode. The addresses and codes differ from those of Byte mode. Refer to "Sector Group Protection Verify Autoselect Codes" in DEVICE BUS OPERATION. Read Mode The device has two control functions required to obtain data at the outputs. CE is the power control and used for a device selection. OE is the output control and used to gate data to the output pins. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time (tOE) is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after power-up, to input hardware reset or to change CE pin from "H" or "L".
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MBM29PL12LM10
Page Mode Read The device is capable of fast read access for random locations within limited address location called page. The page size of the device is 8 bytes / 4 words, within the appropriate page being selected by the higher address bits A22 to A2 and the address bits A1 to A0 in Word mode ( A1 to A-1 in Byte mode) determining the specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The initial page access is equal to the random access (tACC) and subsequent Page read access (as long as the locations specified by the microprocessor fall within that Page) is equivalent to the page address access time(tPACC). Here again, CE selects the device and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast Page mode, accesses are obtained by keeping A20 to A2 constant and changing A1 and A0 in Word mode ( A1 to A-1 in Byte mode ) to select the specific word within that Page. Refer to "Read Operation Timing Diagram" in TIMING DIAGRAM. Output Disable With the OE input at logic high level (VIH), output from the devices are disabled. This may cause the output pins to be in a high impedance state. Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the device function. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever starts later; while data is latched on the rising edge of WE or CE, whichever starts first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Group Protection The device features hardware sector group protection. This feature will disable both program and erase operations in any combination of 70 sector groups of memory.See "Sector Group Address Table (MBM29PL12LM)" in DEVICE BUS OPERATION. The user`s side can use the sector group protection using programming equipment. The device is shipped with all sector groups that are unprotected. To activate it, the programming equipment must force VID on address pin A9 and control pin OE, CE = VIL and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) . The sector group addresses (A22, A21, A20, A19, A18, A17, A16, and A15) should be set to the sector to be protected. "Sector Group Address Table (MBM29PL12LM)" in DEVICE BUS OPERATION defines the sector address for each of the 70 individual sectors, and "Sector Group Address Table (MBM29PL12LM)" in DEVICE BUS OPERATION defines the sector group address for each of the twenty-four (24) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse. See "Sector Group Protection Timing Diagram" in TIMING DIAGRAM and "Sector Group Protection Algorithm" in FLOW CHART for sector group protection timing diagram and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A22, A21, A20, A19, A18, A17, A16, and A15) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical "1" code at device output DQ0 for a protected sector. Otherwise the device will produce "0" for unprotected sectors. In this mode, the lower order addresses, except for A0, A1, A2, A3, and A6 can be either High or Low. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires applying to VIL on Byte mode. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses(A22, A21, A20, A19, A18, A17, A16, and A15) are the desired sector group address will produce a logical "1" at DQ0 for a protected sector group. See "MBM29PL12LM User Bus Operations (Word Mode : BYTE = VIH) and "Sector Group Protection Verify Autoselect Codes" in DEVICE BUS OPERATION for Autoselect codes. 26
MBM29PL12LM10
Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sector groups of the devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to "Temporary Sector Group Unprotection Timing Diagram" in TIMING DIAGRAM and "Temporary Sector Group Unprotection Algorithm" in FLOW CHART. Hardware Reset The devices may be reset by driving the RESET pin to VIL from VIH. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least "tRP" in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode "tREADY" after the RESET pin is driven low. When the RESET pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Furthermore, once the RESET pin goes high, the devices require an additional "tRH" before it will allow read access. Write Protect (WP) The Write Protection function provides a hardware method of protecting certain first 64K bytes / 32K words sector without using VID. This function is one of two provided by the WP/ACC pin. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the first 64K bytes / 32K words sector independently of whether this sector was protected or unprotected using the method described in "Sector Group Protection" above. If the system asserts VIH on the WP/ACC pin, the device reverts of whether the first 64K bytes / 32K words sectors were last set to be protected to the unprotected status. Sector protection or unprotection for this sector depends on whether this was last protected or unprotected using the method described in "Sector protection/ unprotection". Accelerated Program Operation The device offers accelerated program operation which enables programming in high speed. If the system asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 85%. This function is primarily intended to allow high speed programing, so caution is needed as the sector group becomes temporarily unprotected. The system would use a fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device is automatically set to fast mode. Therefore, the present command and sequence could be used for programming and detection of completion during acceleration mode. Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from the WP/ ACC pin while programming. See "Accelerated Program Timing Diagram" in TIMING DIAGRAM. VCCQ
VCCQ determines the MBM29PL12LM voltage output. VCCQ facilitates signal exchange within devices that operate in different voltage.
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MBM29PL12LM10
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. "MBM29PL12LM Standard Command Definitions" in DEVICE BUS OPERATION shows the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h) commands are valid only while the program operation is in progress. Moreover reset commands are functionally equivalent. Please note that commands must be asserted to DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read mode, the Reset operation is initiated by writing the reset command sequence into the command register. The devices remain enabled for reads until the command register contents are altered. The devices will automatically be in the reset state after power-up. In this case, a command sequence is not required in order to read data. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore, manufacture and device codes must be accessible while the devices reside in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However applying high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write cycle that contains the address and the Autoselect command. Then the manufacture and device codes can be read from the address, and an actual data of memory cell can be read from the another address. Following the command write, a read cycle from address 00h returns the manufactures's code (Fujitsu = 04h). A read cycle at address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes at address of 0Eh as well as at 0Fh. Notice that above applies to Word mode. The addresses and codes differ from those of Byte mode. Refer to "Sector Group Protection Verify Autoselect Codes" in DEVICE BUS OPERATION. To terminate the operation, it is necessary to write the reset command into the register. To execute the Autoselect command during the operation, reset command must be written before the Autoselect command. Programming The devices are programmed on a word-by-word basis. Programming is a 4 bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens first) starts programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit) or RY/BY. The Data Polling and Toggle Bit are automatically performed at the memory location being programmed. The programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which the devices return to the read mode and plogram addresses are no longer latched. Therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance. Hence Data Polling requires the same address which is being programmed. If hardware reset occurs during the programming operation, the data being written is not guaranteed.
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MBM29PL12LM10
Programming is allowed in any address sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may result in either failure condition or an apparent success according to the data polling algorithm. But a read from reset command will show that the data is still "0". Only erase operations can convert "0"s to "1"s. Note that attempting to program a "1" over a "0" will result in programming failure. This precaution is the same with Fujitsu standard NOR devices. "Embedded ProgramTM Algorithm" in FLOW CHART illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. Program Suspend/Resume The Program Suspend command allows the system to interrupt a program operation so that data can be read from any address. Writing the Program Suspend command (B0h) during Embedded Program operation immediately suspends the programming. Refer to "Erase Suspend/Resume" for the detail. When the Program Suspend command is written during a programming process, the chip halts the program operation within 1s and suspend the status bits.After the program operation has been suspended, the system can read data from any address. Normal read timing and command definitions apply. The data at programsuspended address is not valid. After the Program Resume command (30h) is written, the chip reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. When issuing program suspend command in 4 s after issuing program command, determine the status of program operation by reading status bit at more 4 s after issuing program resume command. The system also writes the Autoselect command sequence in the Program Suspend mode. The device allows reading Autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. When the device exits the Autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Program Resume command to exit from the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the chip resumes programming. Write Buffer Programming Operations Write Buffer Programming allows the system write to series of 16 words in one programming operation. This results in faster effective word programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initialized by first writing two unlock cycles. This is followed by a third write cycle selecting the Sector Address in which programming will occur. In forth cycle contains both Sector Address and unique code for data bus width will be loaded into the page buffer at the Sector Address in which programming will occur. The system then writes the starting address/data combination. This "starting address" must be the same Sector Address used in third and fourth cycles and its lower addresses of A3 to A0 should be 0h. All subsequent address must be incremented by 000Fh. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens first) starts programming. Upon executing the Write Buffer Programming Operations command sequence, the system is not required to provide further controls. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. DQ7(Data Polling), DQ6(Toggle Bit), DQ5(Exceeded Timing Limits), DQ1(Write-to-Buffer Abort) should be monitored to determine the device status during Write Buffer Programming. In addition to these functions, it is also possible to indicate to the host system that Write Buffer Programming Operations are either in progress or have been completed by RY/BY. See "Hardware Sequence Flags". The Data polling techniques described in "Data Polling Algorithm" in FLOW CHART should be used while monitoring the last address location loaded into the write buffer. In addition, it is not neccessary to specify an address in Toggle Bit techniques described in "Toggle Bit Algorithm" in FLOW CHART. The automatic pro29
MBM29PL12LM10
graming operation is completed when the data on DQ7 is equivalent to the data written to this bit at which time the device returns to the read mode ( See "Hardware Sequence Flags"). The write-buffer programming operation can be suspended/resumed using the standard program suspend/ resume commands. Once the write buffer programming is set, the system must then write the "Program Buffer to Flash" command at the Sector Address. Any other address/data combination will abort the Write Buffer Programming operation and the device will continue busy state. The Write Buffer Programming Sequence can be ABORTED by doing the following : * Different Sector Address is asserted. * Write data other than the "Program Buffer to Flash" command after the specified number of "data load" cycles. A "Write-to-Buffer-Abort Reset" command sequence must be written to the device to return to read mode. (See "MBM29PL12LM Standard Command Definitions" in DEVICE BUS OPERATION for details on this command sequence.) Chip Erase Chip erase is a 6 bus cycle operation. It begins two "unlock" write cycles followed by writing the "set-up" command, and two "unlock" write cycles followed by the chip erase command which invokes the Embedded Erase algorithm. The device does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm the devices automatically programs and verifies the entire memory for an all 0 data pattern prior to electrical erase (Preprogram function). The system is not required to provide any controls or timings during these operations. The system can determine the erase operation status by using DQ7 (Data Polling), DQ6 (Toggle Bit) and DQ2 (Toggle Bit II) or RY/BY output signal. The chip erase begins on the rising edge of the last CE or WE, whichever happens first from last command sequence and completes when the data on DQ7 is "1" at which time the device returns to read mode. Sector Erase Sector erase is a 6 bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. Multiple sectors may be erased concurrently by writing the same six bus cycle operations. This sequence is followed by writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than Erase Time-out time(tTOW). Otherwise that command will not be accepted and erasure will not start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can reoccur after the last Sector Erase command is written. A time-out of "tTOW" from the rising edge of last CE or WE, whichever happens first, will initiate the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the "tTOW" timeout window the timer is reset (monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer). Resetting the devices once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete (refer to the Write Operation Status). Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 255). Sector erase does not require the user to program the devices prior to erase. The devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase using the Embedded Erase Algorithm. When erasing a sector, the remaining unselected sectors remain unaffected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit) or
RY/BY.
The sector erase begins after the "tTOW" time-out from the rising edge of CE or WE whichever happens first for the last sector erase command pulse and completes when the data on DQ7 is "1" (see Write Operation Status section), at which the devices return to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. 30
MBM29PL12LM10
Erase Suspend/Resume The Erase Suspend command allows the user to interrupt Sector Erase operation and then perform read to a sector not being erased. This command is applicable ONLY during the Sector Erase operation within the timeout period for sector erase. Writting the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the "Erase Resume" command resumes the erase operation. When the "Erase Suspend" command is written during the Sector Erase operation, the device takes maximum of "tSPD" to suspend the erase operation. When the devices enter the erase-suspended mode, the RY/BY output pin will be at High-Z and the DQ7 bit will be at logic "1" and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation is suspended, the devices default to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that have not been erase-suspended. Reading successively from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. See the section on DQ2. To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Do not issue program command after entering erase-suspend-read mode. Fast Mode Set/Reset The device has Fast Mode function. It dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming consists of two cycles instead of 4 bus cycles in standard program command. The read operation is also executed after exiting this mode. During the Fast mode, do not write any command other than the Fast program/Fast mode reset command. To exit from this mode, write Fast Mode Reset command into the command register. (Refer to the "Embedded ProgramTM Algorithm for Fast Mode" in FLOW CHART.) The VCC active current is required even CE = VIH during Fast Mode. Fast Programming During Fast Mode, the programming can be executed with 2 bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). See "Embedded ProgramTM Algorithm for Fast Mode" in FLOW CHART.
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MBM29PL12LM10
Extended Sector Group Protection In addition to normal sector group protection, the device has Extended Sector Group Protection as extended function. This function enables protection of the sector group by forcing VID on RESET pin and writes a command sequence. Unlike conventional procedures, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then the sector group addresses pins (A22, A21, A20, A19, A18, A17, A16 and A15) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (set VIL for the other addresses pins is recommended), and write extended sector group protection command (60h). A sector group is typically protected in 250 s. To verify programming of the protection circuitry, the sector group addresses pins (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set and write a command (40h). Following the command write, a logical "1" at device output DQ0 will produce for protected sector in the read operation. If the output data is logical "0", write the extended sector group protection command (60h) again. To terminate the operation, set RESET pin to VIH. (Refer to the "Extended Sector Group Protection Timing Diagram" in TIMING DIAGRAM and "Extended Sector Group Protection Algorithm" in FLOW CHART.) Query Command (CFI : Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98h) into the command register. Following the command write, a read cycle from specific address retrieves device information. Please note that output data of upper byte (DQ15 to DQ8) is "0". Refer to the CFI code table. To terminate operation, it is necessary to write the Reset command sequence into the register. (See "Common Flash Memory Interface Code" in DEVICE BUS OPERATION.)
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MBM29PL12LM10
HiddenROM Mode (1) HiddenROM Region The HiddenROM (HiddenROM) feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the HiddenROM region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The HiddenROM region is 256 bytes / 128 words in length. After the system writes the HiddenROM Entry command sequence, it may read the HiddenROM region by using device addresses A6 to A0 (A22 to A15 are all "0"). That is, the device sends only program command that would normally be sent to the address to the HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the address. If you request Fujitsu to program the ESN in the device, please contact a Fujitsu representative for more information. (2) HiddenROM Entry Command The device has a HiddenROM region with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Programming is allowed in this area until it is protected. However, once it gets protected, it is impossible to unprotect. Therefore, extreme caution is required. The HiddenROM region is 256 bytes / 128 words. This area is in SA0 . Therefore, write the HiddenROM entry command sequence to enter the HiddenROM region. It is called HiddenROM mode when the HiddenROM region appears. Sectors other than the block area SA0 can be read during HiddenROM mode. Read/program of the HiddenROM region is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit the HiddenROM mode. Note that any other commands should not be issued than the HiddenROM program/protection/ reset commands during the HiddenROM mode. When you issue the other commands including the suspend resume capability, send the HiddenROM reset command first to exit the HiddenROM mode and then issue each command. (3) HiddenROM Program Command To program the data to the HiddenROM region, write the HiddenROM program command sequence during HiddenROM mode. This command is the same as the usual program command, except that it needs to write the command during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data pooling, DQ6 Toggle bit or RY/BY. You should pay attention to the address to be programmed. If an address not in the HiddenROM region is selected, the previous data will be deleted. During the write into the HiddenROM region, the program suspend command issuance is prohibited. (4) HiddenROM Protect Command There are two methods to protect the HiddenROM region. One is to write the sector group protect setup command (60h) , set the sector address in the HiddenROM region and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and write the sector group protect command (60h) during the HiddenROM mode. The same command sequence may be used because it is the same as the extension sector group protect in the past, except that it is in the HiddenROM mode and does not apply high voltage to the RESET pin. Please refer to above mentioned "Extended Sector Group Protection" for details of sector group protect setting. The other method is to apply high voltage (VID) to A9 and OE, set the sector address in the HiddenROM region and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and apply the write pulse during the HiddenROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) and the sector address in the HiddenROM region, and read. When "1" appears on DQ0, the protect setting is completed. "0" will appear on DQ0 if it is not protected. Apply write pulse again. The same command sequence could be used for the above method because other than the HiddenROM mode, it is the same as the sector group protect previously mentioned. 33
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Take note that other sector groups will be affected if an address other than those for the HiddenROM region is selected for the sector group address. Pay close attention that once it is protected, protection CANNOT BE CANCELLED. Write Operation Status Detailed in "Hardware Sequence Flags" are all the status flags which can determine the status of the device for current mode operation. When checking Hardware Sequence Flags during program operations, it should be checked 4 s after issuing program command. During sector erase, the part provides the status flags automatically to the I/O ports. The information on DQ2 is address sensitive. If an address from an erasing sector is consecutively read, then the DQ2 bit will toggle. However DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows the user to determine which sectors are erasing. Once erase suspend is entered address sensitivity still applies. If the address of a non-erasing sector (one available for read) is provided, then stored data can be read from the device. If the address of an erasing sector (one unavailable for read) is applied, the device will output its status bits. Hardware Sequence Flags Status Embedded Program Algorithm Embedded Erase Algorithm Program-Suspend-Read Program (Program Suspended Sector) Suspend Program-Suspend-Read Mode (Non-Program Suspended Sector) Erase-Suspend-Read (Erase Suspended Sector) Erase Erase-Suspend-Read Suspend (Non-Erase Suspended Sector) Mode Erase-Suspend-Program (Non-Erase Suspended Sector) Embedded Program Algorithm Exceeded Embedded Erase Algorithm Time Erase Erase-Suspend-Program Limits Suspend (Non-Erase Suspended Sector) Mode BUSY State Write to Buffer*4 Exceeded Timing Limits ABORT State DQ7 DQ7 0 Data Data 1 Data DQ7 DQ7 0 DQ7 DQ7 DQ7 N/A DQ6 Toggle Toggle Data Data 1 Data Toggle Toggle Toggle Toggle Toggle Toggle Toggle DQ5 0 0 Data Data 0 Data 0 1 1 1 0 1 0 DQ3 0 1 Data Data 0 Data 0 0 1 0 N/A N/A N/A DQ2 1 Toggle* Data Data Toggle*1 Data 1*2 1 N/A N/A N/A N/A N/A
1
DQ1*3 0 N/A Data Data N/A Data N/A N/A N/A N/A 0 0 1
In Progress
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. *2 : Reading from non-erase suspend sector address will indicate logic "1" at the DQ2 bit. *3 : DQ1 indicates the Write-to-Buffer ABORT status during Write-Buffer-Programming operations. *4 : The Data Polling algorithm detailed in "Data Polling Algorithm" in FLOW CHART should be used for WriteBuffer-Programming operations. Note that DQ7 during Write-Buffer-Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
34
MBM29PL12LM10
DQ7 Data Polling The devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read devices will produce reverse data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce true data last written to DQ7. For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read device will produce a "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in "Data Polling Algorithm" in FLOW CHART. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write cycles. Data Polling must be performed at sector addresses of sectors being erased, not protected sectors. Otherwise, the status may become invalid. If a program address falls within a protected sector, Data polling on DQ7 is active for approximately 1 s, then the device returns to read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 400 s, then the device returns to read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time, and then that byte's valid data the next. Depending on when the system samples the DQ7 output, it may read the sequence flag or valid data. Even if the device completes the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may still be invalid. The valid data on DQ7 to DQ0 will be read on the successive read attempts. The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend mode or sector erase time-out. See "Data Polling during Embedded Algorithm Operation Timing Diagram" in TIMING DIAGRAM for the Data Polling timing specifications and diagram. DQ6 Toggle Bit I The device also feature the "Toggle Bit I" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data from the devices will result in DQ6 toggling between 1 and 0. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write cycles. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write cycles. The Toggle Bit I is active during the sector time out. In programm operation, if the sector being written to is protected, the Toggle bit will toggle for about 1 s and then stop toggling with the data unchanged. In erase, the device will erase all the selected sectors except for the protected ones. If all selected sectors are protected, the chip will toggle the Toggle bit for about 400 s and then drop back into read mode, having data kept remained. Either CE or OE toggling will cause the DQ6 to toggle. See "Toggle Bit l Timing Diagram during Embedded Algorithm Operations" in TIMING DIAGRAM for the Toggle Bit I timing specifications and diagram.
35
MBM29PL12LM10
DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a "1". This is a failure condition indicating that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the device under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in "MBM29PL12LM User Bus Operations (Word Mode : BYTE = VIH)" and "MBM29PL12LM User Bus Operations (Byte Mode : BYTE = VIL)" in DEVICE BUS OPERATION. The DQ5 failure condition may also appear if a user tries to program a non blank location without pre-erase. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a "1". Note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset the device with command sequence. DQ3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates a valid erase command has been written, DQ3 may be used to determine whether the sector erase timer window is still open. If DQ3 is "1" the internally controlled erase cycle has begun. If DQ3 is "0", the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See "Hardware Sequence Flags". DQ2 Toggle Bit II This Toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase suspended sector will indicate a logic "1" at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows: For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also "Hardware Sequence Flags" and "DQ2 vs. DQ6" in TIMING DIAGRAM. Furthermore, DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles if this bit is read from an erasing sector.
36
MBM29PL12LM10
Reading Toggle Bits DQ6 / DQ2 Whenever the system initially begins reading Toggle bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a Toggle bit is toggling. Typically a system would note and store the value of the Toggle bit after the first read. After the second read, the system would compare the new value of the Toggle bit with the first. If the Toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7 to DQ0 on the following read cycle. However, if, after the initial two read cycles, the system determines that the Toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then determine again whether the Toggle bit is toggling, since the Toggle bit may have stopped toggling just as DQ5 went high. If the Toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the Toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the Toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (Refer to "Toggle Bit Algorithm" in FLOW CHART.) Toggle Bit Status Mode Program Erase Erase-Suspend-Read (Erase-Suspended Sector) Erase-Suspend-Program DQ7 DQ7 0 1 DQ7 DQ6 Toggle Toggle 1 Toggle DQ2 1 Toggle *1 Toggle *1 1 *2
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. *2 : Reading from the non-erase suspend sector address will indicate logic "1" at the DQ2 bit. DQ1 Write-to-Buffer Abort DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a "1". The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See "Write Buffer Programming Operations" section for more details. RY/BY Ready/Busy The device provides a RY/BY open-drain output pin to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with either a program or erase operation. If the output is high impedance, the device is ready to accept any write or erase operation. If the device is placed in an Erase Suspend mode, the RY/BY output will be high, by means of connecting with a pull-up resister. During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a ready condition during the RESET is VIL. See "RY/BY Timing Diagram during Program/Erase Operation Timing Diagram" and "RESET Timing Diagram ( During Embedded Algorithms )" in "TIMING DIAGRAM" for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
37
MBM29PL12LM10
Word/Byte Configuration BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the device. When this pin is driven high, the device operates in the word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this pin is driven low, the device operates in byte (8-bit) mode. In this mode, DQ15/A-1 pin becomes the lowest address bit, and DQ14 to DQ8 bits are High-Z. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Data Protection The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically reset the internal state machine in Read mode. Also, with its command register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise. (1) Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO. If Embedded Erase Algorithm is interrupted, the intervened erasing sector(s) is(are) not valid. (2) Write Pulse "Glitch" Protection Noise pulses of less than 3 s (typical) on OE, CE, or WE will not initiate a write cycle. (3) Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must be low while OE is high. (4) Power-up Write Inhibit Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically set to read mode on power-up. (5) Sector Protection Device is able to protect each sector group to store and protect data in the user side. Protection circuit voids both write and erase commands that are addressed to protected sectors. Any commands to write or erase addressed to protected sector are ignored . See "Sector Group Protection" in FUNCTIONAL DESCRIPTION.
38
MBM29PL12LM10
ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All Pins Except A9, OE, and RESET *1,*2 Power Supply Voltage *1 A9, OE, and RESET * * WP/ACC *1,*3
1, 3
Symbol Tstg TA VIN, VOUT VCC VIN VACC
Rating Min -55 -20 -0.5 -0.5 -0.5 -0.5 Max +125 +85 VCC +0.5 +4.0 +12.5 +12.5
Unit C C V V V V
*1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -0.2 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns *3 : Minimum DC input voltage is -0.5V. During voltage transitions, these pins may undershoot VSS to -0.2 V for periods of up to 20 ns.Voltage difference between input and supply voltage ( VIN-VCC) dose not exceed to +9.0 V. Maximum DC input voltage is +12.5 V which may overshoot to +14.0 V for periods of up to 20 ns . WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
RECOMMENDED OPERATING RANGES*1
Parameter Ambient Temperature VCC Supply Voltage *2, *3 VCCQ Supply Voltage *2, *3 10 Symbol TA VCC VCCQ Value Min -20 +3.0 VCC Max +85 +3.6 Unit C V V
*1 : Operating ranges define those limits between which the functionality of the device is guaranteed. *2 : Voltage is defined on the basis of VSS = GND = 0V. *3 : See if VCC and VCCQ are of the same value. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
39
MBM29PL12LM10
MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
+0.6 V -0.5 V -2.0 V
20 ns
20 ns
20 ns
Maximum Undershoot Waveform
20 ns
VCC +2.0 V VCC +0.5 V 0.7 x VCC
20 ns 20 ns
Maximum Overshoot Waveform 1
20 ns
+14.0 V +12.5 V VCC +0.5 V
20 ns 20 ns
Note: This waveform is applied for A9, OE, RESET, and WP/ACC.
Maximum Overshoot Waveform 2
40
MBM29PL12LM10
ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter Input Leakage Current Output Leakage Current A9, OE, RESET Inputs Leakage Current Symbol ILI ILO ILIT Conditions VIN = VSS to VCC, VCC = VCC Max WP/ACC pin Others Value Min -2.0 -1.0 -1.0 -- -- -- -- -- -- -- Typ -- -- -- -- 15 15 35 35 10 50 Max +2.0 +1.0 +1.0 35 25 25 50 50 20 60 mA mA mA Unit A A A
VOUT = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9, OE, RESET = 12.5 V CE = VIL, OE = VIH, f = 5 MHz Word Byte Word Byte
VCC Active Current (Read ) *1,*2
ICC1 CE = VIL, OE = VIH, f = 10 MHz ICC2 ICC3
VCC Active Current (Intra-Page Read ) *2 VCC Active Current (Program / Erase) *2,*3 VCC Standby Current *2
CE = VIL, OE = VIH, tPRC = 25ns, 4-Word CE = VIL, OE = VIH CE = VCC 0.3 V, RESET = VCC 0.3 V, OE = VIH, WP/ACC = VCC 0.3 V RESET = VCC 0.3 V, WP/ACC = VCC 0.3 V CE = VSS 0.3 V, RESET = VCC 0.3 V, VIN = VCC 0.3V or Vss 0.3V, WP/ACC = VCC 0.3 V CE = VIL, OE = VIH CE = VIL, OE = VIH, WP/ACC pin Vcc = Vcc Max, WP/ACC =VACC Max Vcc Pin -- -- VCC = 3.0 V to 3.6 V
ICC4
--
1
5
A
VCC Reset Current *2
ICC5
--
1
5
A
VCC Automatic Sleep Current *4
ICC6
--
1
5
A
VCC Active Current (Erase-Suspend-Program) *2 ACC Accelerated Program Current Input Low Level Input High Level Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration Voltage for Autoselect, and Temporary Sector Unprotected Output Low Voltage Level Output High Voltage Level Low VCC Lock-Out Voltage
ICC7
-- -- -- -0.5 0.7xVCC 11.5
50 -- -- -- -- 12.0
60 45 60 0.6 VCC + 0.3 12.5
mA
IACC VIL VIH VACC
mA V V V
VID VOL VOH VLKO
VCC = 3.0 V to 3.6 V IOL = 4.0 mA, VCC = VCC Min IOH = -2.0 mA, VCC = VCC Min --
11.5 --
0.85xVCCQ
12.0 -- -- --
12.5 0.45 -- 2.5
V V V V
2.3
41
MBM29PL12LM10
*1 : The lCC current listed includes both the DC operating current and the frequency dependent component. *2 : ICC peaks when both VCC and VCCQ are at their Max. *3 : ICC active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress. *4 : Automatic sleep mode enables the low power mode when address remain stable for tACC + 30 ns.
42
MBM29PL12LM10
2. AC Characteristics
* Read Only Operations Characteristics Parameter Read Cycle Time Address to Output Delay Chip Enable to Output Delay Page Read Cycle Time Page Address to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable Read Hold Time Toggle and Data Polling Output Enable to Output High-Z Output Hold Time From Addresses, CE or OE, Whichever Occurs First RESET Pin Low to Read Mode tAVAV tAVQV tELQV -- -- tGLQV tEHQZ -- tGHQZ tAXQX -- Symbols JEDEC Standard tRC tACC tCE tPRC tPACC tOE tDF tOEH tDF tOH tREADY -- CE = VIL, OE = VIL OE = VIL -- CE = VIL, OE = VIL -- -- -- -- -- -- -- Value* Condition Min 100 25 0 10 0 10 Max 100 100 30 30 25 25 20 ns ns ns ns ns ns ns ns ns ns ns s Unit
* : Test Conditions : Output Load : 1 TTL gate and 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V or VCC Timing measurement reference level Input : VCC / 2 Output : VCC / 2 * Output load circuit
3.3 V Diode = 1N3064 or Equivalent Device Under Test 6.2 k CL Diode = 1N3064 or Equivalent
2.7 k
Test Conditions
43
MBM29PL12LM10
* Write (Erase/Program) Operations Parameter JEDEC Write Cycle Time Address Setup Time Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CE or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Setup Time CE High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write (OE High to WE Low) Read Recover Time Before Write (OE High to CE Low) CE Setup Time WE Setup Time CE Hold Time WE Hold Time CE Pulse Width Write Pulse Width CE Pulse Width High Write Pulse Width High Effective Page Programming Time Per Word (Write Buffer Programming) Programming Time Sector Erase Operation * VCC Setup Time Recovery Time From RY/BY Erase/Program Valid to RY/BY Delay Rise Time to VID *
2 1
Symbol Standard tWC tAS tASO tAH tAHT tDS tDH tOES tCEPH tOEPH tGHWL tGHEL tCS tWS tCH tWH tCP tWP tCPH tWPH Min 100 0 15 45 0 45 0 0 20 20 0 0 0 0 0 0 35 35 25 30 tWHWH2 -- -- -- -- -- -- tWHWH2 tVCS tPB tBUSY tVIDR tVACCR tVLHT 50 0 500 500 4
Value 10 Typ 23.5 100 1.0 Max 90 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s ns ns ns ns s (Continued) Unit
tAVAV tAVWL -- tWLAX -- tDVWH tWHDX -- -- -- tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tELEH tWLWH tEHEL tWHWL
tWHWH1
tWHWH1
Word
Rise Time to VACC *3 Voltage Transition Time *2
44
MBM29PL12LM10
(Continued) Parameter JEDEC Write Pulse Width *2 OE Setup Time to WE Active * CE Setup Time to WE Active * RESET Pulse Width RESET High Time Before Read Delay Time from Embedded Output Enable Erase Time-out Time Erase Suspend Transition Time
2 2
Symbol Standard tWPP tOESP tCSP tRP tRH tEOE tTOW tSPD Min 100 4 4 500 100 50
Value 10 Typ Max 100 20 s s s ns ns ns s s Unit
-- -- -- -- -- -- -- --
*1 : This does not include the preprogramming time. *2 : This timing is for Sector Group Protection operation. *3 : This timing is for Accelerated Program operation.
45
MBM29PL12LM10
ERASE AND PROGRAMMING PERFORMANCE
Parameter Limits Min -- -- -- -- -- 100,000 Typ 1 100 23.5 -- -- -- Max 15 3000 -- 1200 6 -- Unit Remarks Excludes programming time prior to erasure
Sector Erase Time Programming Time Effective Page Programming Time (Write Buffer Programming) Chip Programming Time Absolute Maximum Programming Time (16 words) Erase/Program Cycle
s s s s ms cycle
Excludes system-level overhead
Non programming within the same page --
TSOP (1) PIN CAPACITANCE
Parameter Input Capacitance Output Capacitance Control Pin Capacitance Reset pin and WP/ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 Test Setup VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Value Typ 8 8.5 8 20 Max 10 12 10 25 Unit pF pF pF pF
Notes : * Test conditions TA = +25C, f = 1.0 MHz * DQ15/A-1 pin capacitance is stipulated by output capacitance.
FBGA PIN CAPACITANCE
Parameter Input Capacitance Output Capacitance Control Pin Capacitance Reset pin and WP/ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 Test Setup VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Value Typ 8 8.5 8 15 Max 10 12 10 20 Unit pF pF pF pF
Notes : * Test conditions TA = +25C, f = 1.0 MHz * DQ15/A-1 pin capacitance is stipulated by output capacitance.
46
MBM29PL12LM10
TIMING DIAGRAM
* Key to Switching Waveforms
WAVEFORM INPUTS Must Be Steady May Change from H to L May Change from L to H "H" or "L" Any Change Permitted Does Not Apply OUTPUTS Will Be Steady Will Be Changing from H to L Will Be Changing from L to H Changing State Unknown Center Line is HighImpedance "Off" State
tRC
Address
Address Stable
tACC
CE
tOE tDF
OE
tOEH
WE
tCE tOH
Data
High-Z
Output Valid
High-Z
Read Operation Timing Diagram
47
MBM29PL12LM10
A22 to A2 A1 to A0 (A-1)
Address Valid
Aa tRC tACC
Ab tPRC
Ac
CE
tCE
OE
tOEH
tOE tDF
WE Data High-Z
tPACC tOH Da
tPACC tOH Db tOH Dc
Page Read Operation Timing Diagram
tRC
Address
tACC
Address Stable
CE
tRH
tRP
tRH
tCE
RESET
tOH
Data
High-Z
Output Valid
Hardware Reset/Read Operation Timing Diagram 48
MBM29PL12LM10
3rd Bus Cycle Address
555h tWC tAS PA tAH
Data Polling
PA tRC
CE
tCS tCH tCE
OE
tGHWL tWP tWPH tWHWH1 tOE
WE
tDS tDH tDF tOH
Data
A0h
PD
DQ7
DOUT
DOUT
Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at word address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates the last two bus cycles out of four bus cycle sequence.
Alternate WE Controlled Program Operation Timing Diagram
49
MBM29PL12LM10
3rd Bus Cycle
Data Polling PA tAS tAH PA
Address
555h tWC
WE
tWS tWH
OE
tGHEL tCP tCPH tWHWH1
CE
tDS tDH
Data
A0h
PD
DQ 7
D OUT
Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at word address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates the last two bus cycles out of four bus cycle sequence.
Alternate CE Controlled Program Operation Timing Diagram
50
MBM29PL12LM10
Address
555h tWC
2AAh tAS tAH
555h
555h
2AAh
SA*
SA*
CE
tCS tCH
OE
tGHWL tWP tWPH tTOW
WE
tDS AAh tDH 55h 80h AAh 55h
10h for Chip Erase 10h/ 30h tBUSY 30h
Data
RY/BY
tVCS
VCC
* : SA is the sector address for Sector Erase. Address = 555h (Word), AAAh (Byte) for Chip Erase.
Chip/Sector Erase Operation Timing Diagram
51
MBM29PL12LM10
Address
XXXh tWC
CE
tCS tWP tCH
WE
tDS B0h tSPD
Data RY/BY
Erase Suspend Operation Timing Diagram
52
MBM29PL12LM10
Address
VA
CE
tCH
tOE
tDF
OE
tOEH
WE
4 s tCE *
DQ7
Data
DQ7
DQ7 = Valid Data
High-Z
tWHWH1 or 2
DQ6 to DQ0
Data tBUSY
DQ6 to DQ0 = Output Flag tEOE
DQ6 to DQ0 Valid Data
High-Z
RY/BY
* : DQ7 = Valid Data (The device has completed the Embedded operation.) Note : When checking Hardware Sequence Flags during program operations, it should be checked 4 s after issuing program command. Data Polling during Embedded Algorithm Operation Timing Diagram
53
MBM29PL12LM10
Address
tAHT tASO tAHT tAS
CE
tCEPH
WE
4 s
tOEPH tOEH
OE
tDH tOE tCE
DQ 6/DQ2
Data
tBUSY
Toggle Data
Toggle Data
Toggle Data
*
Stop
Toggling
Output Valid
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation). Note : When checking Hardware Sequence Flags during program operations, it should be checked 4 s after issuing program command. Toggle Bit Timing Diagram during Embedded Algorithm Operations
Enter Embedded Erasing WE
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2* Toggle DQ2 and DQ6 with OE or CE
* : DQ2 is read from the erase-suspended sector. DQ2 vs. DQ6
54
MBM29PL12LM10
CE
Rising edge of the last WE signal
WE
Entire programming or erase operations
RY/BY
tBUSY
RY/BY Timing Diagram during Program/Erase Operation Timing Diagram
CE, OE
tRH
RESET
tRP tREADY
RESET Timing Diagram (Not during Embedded Algorithms)
55
MBM29PL12LM10
WE
RESET
tRP tRB
RY/BY
tREADY
RESET Timing Diagram (During Embedded Algorithms)
56
MBM29PL12LM10
A22, A21, A19, A18, A17, A16, A15
SGAX
SGAY
A6, A3, A2, A0
A1
VID VIH A9
t VLHT
VID VIH OE
t VLHT t WPP t VLHT t VLHT
WE
t OESP
CE
t CSP
Data
t VCS t OE
01h
VCC
SGAX : Sector Group Address to be protected SGAY : Next Sector Group Address to be protected
Sector Group Protection Timing Diagram
57
MBM29PL12LM10
VCC
tVCS tVIDR
tVLHT
VID VSS, VIL or VIH RESET
CE
WE
tVLHT RY/BY
Program or Erase Command Sequence
tVLHT
Unprotection period
Temporary Sector Group Unprotection Timing Diagram
58
MBM29PL12LM10
VCC
tVCS
RESET tVLHT tVIDR Add SGAX SGAX SGAY
A6, A3, A2, A0
A1
CE
OE TIME-OUT
WE
Data
60h
60h
40h tOE
01h
60h
SGAX: Sector Group Address to be protected SGAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 s (Min)
Extended Sector Group Protection Timing Diagram
59
MBM29PL12LM10
VCC tVCS VACC ACC
tVACCR tVLHT
CE
WE tVLHT Program Command Sequence tVLHT
Acceleration period
Accelerated Program Timing Diagram
60
MBM29PL12LM10
FLOW CHART
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence (See Below)
Data Polling Embedded Program Algorithm in progress
No
Verify Data ? Yes
Increment Address
No
Last Address ? Yes
Programming Completed
Program Command Sequence (Address/Command): 555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
Note : The sequence is applied for Word ( x16 ) mode. The addresses differ from Byte ( x 8 ) mode. Embedded ProgramTM Algorithm
61
MBM29PL12LM10
EMBEDDED ALGORITHMS
Start
Write Erase Command Sequence (See Below)
Data Polling Embedded Erase Algorithm in progress
No
Data = FFh ? Yes Erasure Completed
Chip Erase Command Sequence (Address/Command): 555h/AAh
Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h Sector Address /30h Sector Address /30h Sector Address /30h
555h/10h
Additional sector erase commands are optional.
Note : The sequence is applied for Word ( x16 ) mode. The addresses differ from Byte ( x 8 ) mode.
Embedded EraseTM Algorithm
62
MBM29PL12LM10
Start
Wait 4 s after issuing Program Command Read Byte (DQ 7 to DQ 0) Addr. = VA
DQ 7 = Data? No No DQ 5 = 1? Yes Read Byte (DQ 7 to DQ 0) Addr. = VA
Yes
VA = Valid address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation = Any of the sector addresses within the sector not being protected during chip erase operation
DQ 7 = Data? * No Fail
Yes
Pass
* : DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Data Polling Algorithm
63
MBM29PL12LM10
Start Wait 4 s after issuing Program Command Read DQ7 to DQ0 Addr. = "H" or "L" Read DQ7 to DQ0 Addr. = "H" or "L" *1
*1
DQ6 = Toggle
No
?
Yes No DQ5 = 1? Yes *1, *2 Read DQ7 to DQ0 Addr. = "H" or "L" *1, *2 Read DQ7 to DQ0 Addr. = "H" or "L"
DQ6 = Toggle ? Yes Program/Erase Operation Not Complete.Write Reset Command
No
Program/Erase Operation Complete
*1 : Read Toggle bit twice to determine whether it is toggling. *2 : Recheck Toggle bit because it may stop toggling as DQ5 changes to "1". Toggle Bit Algorithm
64
MBM29PL12LM10
Start
Setup Sector Group Addr. (A22, A21, A20, A19, A18, A17, A16, A15) PLSCNT = 1 OE = VID, A9 = VID CE = VIL, RESET = VIH A6 = A3 = A2 = A0 = VIL, A1 = VIH
Activate WE Pulse Increment PLSCNT Time out 100 s
WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector Group Addr. = SGA, A1 = VIH A6 = A3 = A2 = A0 = VIL Data = 01h? Yes Protect Another Sector Group? No Device Failed Remove VID from A9 Write Reset Command Yes
(
No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command No
)
Sector Group Protection Completed
* : A-1 is VIL in Byte ( x 8 ) mode.
Sector Group Protection Algorithm
65
MBM29PL12LM10
Start
RESET = VID *1
Perform Erase or Program Operations
RESET = VIH
Temporary Sector Group Unprotection Completed *2
*1 : All protected sector groups are unprotected. *2 : All previously protected sector groups are protected.
Temporary Sector Group Unprotection Algorithm
66
MBM29PL12LM10
Start
RESET = VID
Wait to 4 s
Device is Operating in Temporary Sector Group Unprotection Mode
No
Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXh/60h
PLSCNT = 1
To Protect Sector Group Write 60h to Sector Address
(A6 = A3 = A2 = A0 =VIL, A1 = VIH)
Increment PLSCNT
Time Out 250 s Setup Next Sector Group Address
To Verify Sector Group Protection Write 40h to Sector Address (A6 = A3 = A2 = A0 =VIL, A1 = VIH)
Read from Sector Group Address (A6 = A3 = A2 = A0 =VIL, A1 = VIH) No No PLSCNT = 25? Yes Remove VID from RESET Write Reset Command Data = 01h? Yes Yes Protection Other Sector Group ? No Device Failed Remove VID from RESET Write Reset Command
Sector Group Protection Completed
Extended Sector Group Protection Algorithm
67
MBM29PL12LM10
FAST MODE ALGORITHM
Start
555h/AAh
2AAh/55h
Set Fast Mode
555h/20h
XXXh/A0h
Program Address/Program Data
Data Polling
Verify Data? Yes No
No
In Fast Program
Increment Address
Last Address ? Yes Programming Completed
XXXh/90h Reset Fast Mode XXXh/F0h
Notes : * The sequence is applied for Word ( x16 ) mode. * The addresses differ from Byte ( x 8 ) mode.
Embedded ProgramTM Algorithm for Fast Mode
68
MBM29PL12LM10
ORDERING INFORMATION
Part No. MBM29PL12LM10PCN Package 56-pin, plastic TSOP (1) (FPT-56P-M01) (Normal Bend) 80-ball,plastic FBGA (BGA-80P-M02) Access Time 100 ns Remarks
MBM29PL12LM10PBT
100 ns
MBM29PL12LM
10
PCN PACKAGE TYPE PCN = 56-Pin Thin Small Outline Package (TSOP(1)) Standard Pinout PBT = 80-ball Fine Pitch ball Grid Array Package (FBGA)
SPEED OPTION 10 = 100 ns access time
DEVICE NUMBER/DESCRIPTION 128 Mega-bit (16M x 8/8M x 16) MirrorFlash with Page Mode, Boot Sector 3.0 V-only Read, Program, and Erase
69
MBM29PL12LM10
PACKAGE DIMENSIONS
56-pin plastic TSOP(1) (FPT-56P-M01) Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max) . Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder.
0.100.05 (.004.002) (Stand off)
56
LEAD No.
1
INDEX 0.220.05 (.009.002) *1 14.000.10 (.551.004)
0.10(.004)
M
0.50(.020)
28
29
Details of "A" part 20.000.20(.787.008) *2 18.400.10(.724.004) 0.170.03 .007.001 1.10 -0.05
+0.10 +.004
.043 -.002 (Mounting height)
0~8 0.600.15 (.024.006) 0.25(.010)
0.08(.003)
"A"
C
2002 FUJITSU LIMITED F56001S-c-4-5
Dimensions in mm (inches). Note : The values in parentheses are reference values. (Continued)
70
MBM29PL12LM10
(Continued) 80-ball, plastic FBGA (BGA-80P-M02)
13.000.10(.512.004)
1.08 -0.13 .043 -.005
+0.12 +.005
(Mounting height)
B 0.40(.016) REF 0.80(.031) REF
0.380.10 (Stand off) (.015.004)
A 10.000.10 (.394.004) 0.10(.004) S
8 7 6 5 4 3 2 1
S INDEX AREA
(INDEX AREA) MLKJHGFEDCBA 80-o0.450.05 (80-o.018.002) 0.08(.003)
M
SAB
C
2003 FUJITSU LIMITED B80002S-c-1-1
Dimensions in mm (inches). Note : The values in parentheses are reference values.
71
MBM29PL12LM10
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94088-3470, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ F0405 (c) FUJITSU LIMITED Printed in Japan
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non infringement of any third party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.

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